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1 ltc1406 low power, 8-bit, 20msps, sampling a/d converter the ltc 1406 is a 20msps, 8-bit, sampling a/d converter which draws only 150mw from a single 5v supply. thiseasy-to-use device includes a high dynamic range sample- and-hold with a 250mhz bandwidth. the ltc1406? full-scale input range is 1v. the inputs can be driven differentially or one input can be tied to afixed voltage and the other input driven with a 1v bipolar input. maximum dc specifications include 1lsb dnl and inl over temperature. outstanding ac performanceincludes 48.5db s/(n + d) and 62db thd with a 1mhz input; 47.5db s/(n + d) and 59db thd at the nyquist input frequency of 10mhz. the unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 250mhz bandwidth. the 60db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the adc has an 8-bit parallel output port with separate power supply and ground allowing easy interface to 3v digital systems. the pipelined architecture has five clock cycles of data latency. descriptio n u features low power, 8-bit, 20msps adc 250mhz internal sample-and-hold 7 effective bits at 70mhz input frequency 1lsb dnl and inl max single 5v supply and 150mw dissipation power down to 1 a true differential inputs reject common mode noise accepts single-ended or differential input signals 1v differential or 2v single-ended input span analog inputs common mode to v dd and gnd 24-pin narrow ssop package , ltc and lt are registered trademarks of linear technology corporation. typical applicatio n u low power, 20mhz, 8-bit sampling adc input frequency (hz) effective bits s/(n + d) (db) 2 4 6 100k 1m 10m 100m 1406 ta02 0 3 5 71 85 0 4438 32 effective bits and signal-to-noise + distortion vs input frequency applicatio n s u telecommunications wireless communications digital cellular telephones ccds and image scanners video digitizing and digital television digital color copiers high speed undersampling personal computer video high speed data acquisition track-and- hold amp digital data 8-bit pipeline adc 2.5k av dd v bias v ref ov dd dv dd ognd agnd agnd shdn 1.95k 2.2v output drivers of/ufd7 d6 d5 d4 d3 d2 d1 d0 1406 bd clock circuitry clk a in + 78 94 1 03 56 1 23 2 11 12 2221 20 19 18 17 16 15 24 a in dgnd downloaded from: http:///
2 ltc1406 absolute m axi m u m ratings w ww u package/order i n for m atio n w u u av dd = ov dd = dv dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 6v analog input voltage (note 3) .... ?0.3v to (v dd + 0.3v) digital input voltage (note 4) .................. ?0.3v to 10v digital output voltage ................. ?0.3v to (v dd + 0.3v) power dissipation .............................................. 500mw ambient operation temperature range ltc1406c................................................ 0 c to 70 c ltc1406i ............................................ 40 c to 85 c storage temperature range ................. 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number consult factory for military grade parts. ltc1406cgnltc1406ign 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 ognd ov dd shdn v bias v ref agnd a in + a in av dd agnd dgnd dv dd clk of/uf d7 d6 d5 d4 d3 d2 d1 d0 nc nc t jmax = 110 c, ja = 85 c/ w cc hara terist ics co u verter the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. parameter conditions min typ max units resolution (no missing codes) 8 bits integral linearity error (note 7) 0.5 1 lsb differential linearity error 0.25 1 lsb offset error (note 8) 1 8 lsb gain error with external 2.5v reference 1 5 lsb (notes 5, 6) the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. put u i a a u log (note 5) symbol parameter conditions min typ max units v in analog input span [(a in + ) ?(a in )] (note 9) 4.75v v dd 5.25v 1v input (a in + or a in ) range voltage on either a in + or a in 0v dd v i in analog input leakage current clk = 0 5 a c in analog input capacitance clk = 1 4 pf clk = 0 2 pf input bandwidth 250 mhz t ap sample-and-hold aperture delay time 3 ns t jitter sample-and-hold aperture delay time jitter 5 ps rms cmrr analog input common mode rejection ratio 2.5v < (a in = a in + ) < 2.5v 60 db v bias internal bias voltage no load 2.2 v downloaded from: http:///
3 ltc1406 accuracy ic dy u w a the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 5) symbol parameter conditions min typ max units s/(n + d) signal-to-noise plus distortion ratio 1mhz input signal 48.5 db 10mhz input signal 47.5 db thd total harmonic distortion 1mhz input signal, first 5 harmonics 62 db 10mhz input signal, first 5 harmonics 59 db sfdr spurious free dynamic range 1mhz input signal 63 db 10mhz input signal 60 db imd intermodulation distortion f in1 = 3.500977mhz, f in2 = 3.598633mhz 60 db symbol parameter conditions min typ max units av dd analog positive supply voltage (note 10) 4.75 5.25 v dv dd digital positive supply voltage (note 10) 4.75 5.25 v ov dd output positive supply voltage (note 10) 2.7 5.25 v v bias internal bias voltage when externally driven (note 10) 1.9 2.2 2.5 v v ref reference voltage (note 10) 2 2.5 3 v ognd output ground (note 10) 0 2 v i dd positive supply current av dd = dv dd = ov dd = 5v, f smpl = 20mhz (note 13) 30 45 ma p d power dissipation 150 225 mw power down positive supply current shdn = 0v, clk = v dd or 0 1 10 a power down power dissipation shdn = 0v, clk = v dd or 0 5 50 w (note 5) the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. digital i puts a n d outputs u u (note 5) the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. power require e ts w u symbol parameter conditions min typ max units v ih high level input voltage v dd = 5.25v 2.4 v v il low level input voltage v dd = 4.75v 0.8 v i in digital input current v in = 0v to v dd 5 a c in digital input capacitance 5p f v oh high level output voltage v dd = 4.75v, i o = 10 a 4.5 v v dd = 4.75v, i o = 200 a 4.0 v v ol low level output voltage v dd = 4.75v, i o = 160 a 0.05 v v dd = 4.75v, i o = 1.6ma 0.10 0.4 v i source output source current v out = 0v 20 ma i sink output sink current v out = v dd 30 ma downloaded from: http:///
4 ltc1406 ti i g characteristics w u the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 5) symbol parameter conditions min typ max units f smpl(max) maximum sampling frequency 20 mhz t 1 clock period (notes 11, 12) 50 ns t 2 pulse width high (notes 11, 12) 25 ns t 3 pulse width low (notes 11, 12) 25 ns t 4 output delay c l = 15pf 15 25 ns t 5 pipeline delay 5 cycles t 6 aperture delay 3n s aperture jitter 5p s rms note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: all voltage values are with respect to ground with dgnd, ognd and agnd wired together (unless otherwise noted).note 3: when these pin voltages are taken below ground or above v dd , they will be clamped by internal diodes. this product can handle inputcurrents greater than 100ma below ground or above v dd without latchup. note 4: when these pin voltages are taken below ground they will be clamped by internal diodes. this product can handle input currents up to100ma below ground without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f smpl = 20mhz and t r = t f = 2ns unless otherwise specified.note 6: linearity, offset and full-scale specifications apply for a single- ended a in + input with a in tied to v ref = 2.5v. note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve.the deviation is measured from the center of the quantization band. note 8: bipolar offset is the offset voltage measured from 0.5lsb when the output code flickers between 0111 1111 and 1000 0000.note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: the falling clk edge starts a conversion. note 12: at the maximum conversion rate, deviation from a 50% duty cycle results in interstage settling times < 25ns and performance may be affected. note 13: v in = full scale. distortion vs input frequency typical perfor m a n ce characteristics uw input frequency (hz) 100k s/(n + d) (db) 52 48 44 40 36 32 28 24 20 16 12 8 4 0 1m 10m 100m 1406 g01 s/(n + d) vs input frequency input frequency (hz) 100k amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 1m 10m 100m 1406 g03 thd 3rd harmonic 2nd harmonic signal-to-noise ratio vsinput frequency input frequency (hz) 100k signal-to-noise ratio (db) 52 48 44 40 36 32 28 24 20 16 12 8 4 0 1m 10m 100m 1406 g02 downloaded from: http:///
5 ltc1406 typical perfor m a n ce characteristics uw output code 0 inl eoc error (lsb) 256 1406 g07 64 128 192 1.0 0.5 0 0.5 1.0 32 96 160 224 supply current vssampling frequency sampling frequency (hz) 100k supply current (ma) 35 30 25 20 15 10 5 0 1m 10m 1406 g09 20m input frequency (hz) 100k spurious-free dynamic range (db) 70 60 50 40 30 20 10 0 1m 10m 100m 1406 g04 intermodulation distortion plot frequency (mhz) 0 10 20 30 40 50 60 70 80 90 100 amplitude (db) 1406 g05 0123 4 5 67 8910 f sample = 20mhz f in1 = 3.500977mhz f in2 = 3.598633mhz differential nonlinearityvs output code output code 0 dnl eoc error (lsb) 256 1406 g06 64 128 192 1.0 0.5 0 0.5 1.0 32 96 160 224 input frequency (hz) 100k common mode rejection (db) 70 60 50 40 30 20 10 0 1m 10m 100m 1406 g08 input common mode rejectionvs input frequency integral nonlinearityvs output code spurious-free dynamic rangevs input frequency pi n fu n ctio n s uuu ognd (pin 1): digital data output ground. tie to analog ground plane. may be tied to logic ground if desired. ov dd (pin 2): digital data output supply. normally tied to 5v, can be used to interface with 3v digital logic. bypassto ognd with 10 f tantalum in parallel with 0.1 f or 10 f ceramic.shdn (pin 3): power shutdown input. logic low selects shutdown. v bias (pin 4): internal bias voltage. internally set to 2.2v. bypass to analog ground plane with 10 f tantalum in par- allel with 0.1 f or 10 f ceramic. v ref (pin 5): external 2.5v reference input. bypass to analog ground plane with 10 f tantalum in parallel with 0.1 f or 10 f ceramic. agnd (pin 6): analog ground. tie to analog ground plane. a in + (pin 7): 1v input. the maximum output code occurs when [(a in + ) ?(a in )] = 1v. the minimum output code occurs when [(a in + ) ?(a in )] = 1v. a in (pin 8): 1v input. the maximum output code occurs when [(a in + ) ?(a in )] = 1v. the minimum output code occurs when [(a in + ) ?(a in )] = 1v. for single- ended operation, tie a in to a dc voltage (e.g., v ref ). downloaded from: http:///
6 ltc1406 pi n fu n ctio n s uuu av dd (pin 9): analog 5v positive supply. bypass to ana- log ground plane with 10 f tantalum in parallel with 0.1 f or 10 f ceramic. agnd (pin 10): analog ground. tie to analog ground plane. dgnd (pin 11): digital ground for internal logic. tie to analog ground plane.dv dd (pin 12): digital 5v positive supply. bypass to dgnd with 10 f tantalum in parallel with 0.1 f or 10 f ceramic. nc (pins 13, 14): no internal connection. d7 to d0 (pins 15 to 22): digital data outputs. the out- puts swing between ov dd and ognd. of/uf (pin 23): overflow/underflow bit. of/uf high with d7 to d0 all high indicates an overrange, of/uf high withd7 to d0 all low indicates an underrange condition. of/uf low indicates a conversion within the normal input range. the outputs swing between ov dd and ognd. clk (pin 24): clock input. internal sample-and-hold tracks the input signal when clk is high and samples the inputsignal on the falling edge. av dd = dv dd = v dd nominal (v) absolute maximum (v) pin name description min typ max min max 1 ognd ground for output drivers 0 0.3 v dd + 0.3 2o v dd supply for output drivers 2.7 3 or 5 5.25 0.3 6 3 shdn shutdown input, active low 0 v dd 0.3 10 4v bias internal bias voltage 1.9 2.2 2.5 0.3 v dd + 0.3 5v ref external reference input 2 2.5 3 0.3 v dd + 0.3 6 agnd analog ground, clean ground 0 0.3 v dd + 0.3 7a in + positive analog input, 1v span 0 v dd 0.3 v dd + 0.3 8a in negative analog input 0 v dd 0.3 v dd + 0.3 9a v dd analog supply 4.75 5 5.25 0.3 6 10 agnd analog ground, substrate ground 0 0.3 v dd + 0.3 11 dgnd digital ground 0 0.3 v dd + 0.3 12 dv dd digital supply 4.75 5 5.25 0.3 6 13 to 14 nc no connect, no internal connection 15 to 22 d7 to d0 data outputs ognd ov dd 0.3 v dd + 0.3 23 of/uf overflow/underflow output ognd ov dd 0.3 v dd + 0.3 24 clk clock input 0 v dd 0.3 10 ti i g diagra u w w analog signal clock n ?1 n ?6 n ?5 n ?4 n ?3 n ?2 n ?1 n 1406 td n t 6 n + 1 data out t 3 t 1 t 2 n + 2 n + 3 n + 4 n + 6 n + 5 t 4 t 5 downloaded from: http:///
7 ltc1406 fu n ctio n al block diagra uu w applicatio n s i n for m atio n wu u u conversion detailsthe ltc1406 uses an internal sample-and-hold circuit and a pipeline quantizing architecture to convert an analog signal to an 8-bit parallel output. with clk high the input switches are closed and the analog input will be acquired on the input sampling capacitors c s (see figure 1). on the falling edge of clk the input switches open, captur-ing the input signal. the sampling capacitors are then shorted together and the charge is transferred to the hold track-and- hold amp digital data 8-bit pipeline adc 2.5k av dd v bias v ref ov dd dv dd ognd agnd agnd shdn 1.95k 2.2v output drivers of/ufd7 d6 d5 d4 d3 d2 d1 d0 1406 bd clock circuitry clk a in + 78 94 1 03 56 1 23 2 11 12 2221 20 19 18 17 16 15 24 a in dgnd + c h clk clk 1406 f01 clk to next stage clk clk a in + a in c h c s c s clk figure 1. input sample-and-hold amplifier capacitors c h resulting in a differential dc voltage on the output of the track-and-hold amplifier that is proportionalto the input signal. this differential voltage is fed into a comparator that determines the most significant bit and subtracts the result. the residue is then amplified by two and passed to the next stage via a similar sample-and-hold circuit. this continues down the eight pipeline stages. the comparator outputs are then combined in a digital error correction circuit. the 8-bit word is available at the output, five clock cycles after the sampling edge. dynamic performance the ltc1406 has excellent wideband sampling capability. the sample-and-hold amplifier has a small-signal input bandwidth of 250mhz allowing the adc to undersample input signals with frequencies well beyond the converter? nyquist frequency. fft (fast fourier transform) test tech- niques are used to test the adc? frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adc? spectral content can be examined for frequencies outside the fundamental. figure 2 shows a typical ltc1406 fft plot. downloaded from: http:///
8 ltc1406 where enob is the effective number of bits and s/(n + d)is expressed in db. at the maximum sampling rate of 20mhz the ltc1406 maintains near ideal enobs up to and be- yond the nyquist input frequency of 10mhz (see figure 3). applicatio n s i n for m atio n wu u u frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 amplitude (db) 1406 f02a 0123 4 5 67 8910 f sample = 20mhz f in1 = 1.000977mhz sfdr = 64.8db sinad = 48.6db figure 2a. nonaveraged, 4096 point fftinput frequency = 1mhz signal-to-noise ratiothe signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling fre- quency. the effective number of bits (enobs) is a mea- surement of the resolution of an adc and is directly related to the s/(n + d) by the equation: enob = [s/(n + d) ?1.76]/6.02 figure 2b. nonaveraged, 4096 point fftinput frequency = 30mhz total harmonic distortiontotal harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd vv = +++ 20 3 2 4 2 log v . . .v v 2 2 n 2 1 where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the sec- ond through n th harmonics. thd vs input frequency is shown in figure 4. the ltc1406 has good distortion per-formance up to the nyquist frequency and beyond. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different fre- quency (see figure 5). input frequency (hz) effective bits s/(n + d) (db) 2 4 6 100k 1m 10m 100m 1406 ta02 0 3 5 71 85 0 4438 32 figure 3. effective bits and signal-to-(noise + distortion)vs input frequency frequency (hz) 0 10 20 30 40 50 60 70 80 90 100 amplitude (db) 1406 f02b 0123 4 5 67 8910 f sample = 20mhz f in1 = 28.99902mhz sfdr = 54.9db sinad = 47.0db downloaded from: http:///
9 ltc1406 applicatio n s i n for m atio n wu u u if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer func-tion can create distortion products at the sum and differ- ence frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a f b ). if the two input sine waves are equal in magnitude, thevalue (in decibels) of the 2nd order imd products can be expressed by the following formula: imd f f f amplitude at ab b () = () 20 log amplitude at f f a a peak harmonic or spurious noisethe peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in decibel relative to the rms value of a full-scale input signal (see figure 6). input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the ltc1406 has been designed for wide input bandwidth (250mhz), allowing the adc to undersample input signals with frequencies above the converter? nyquist frequency. the noise floor stays very low at high frequencies; s/(n + d) becomes dominated by distortion at frequencies far beyond nyquist. analog inputs the ltc1406 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. the a in + and a in inputs are sampled at the same time and the adc willalways convert the difference of [(a in + ) ?(a in )] indepen- dent of the common mode voltage. any unwanted signalthat is common to both inputs will be rejected by the com- mon mode rejection of the sample-and-hold circuit. the common mode rejection holds up to extremely high fre- quencies (see figure 7). the inputs can be driven differentially or single-ended. indifferential mode, both inputs are driven 0.5v out of phase with each other. in single-ended mode, the nega-tive input is tied to a fixed voltage and a in + is used as the figure 6. spurious-free dynamic range vsinput frequency input frequency (hz) 100k spurious-free dynamic range (db) 70 60 50 40 30 20 10 0 1m 10m 100m 1406 g04 input frequency (hz) 100k amplitude (db below the fundamental) 0 10 20 30 40 50 60 70 80 1m 10m 100m 1406 g03 thd 3rd harmonic 2nd harmonic figure 4. distortion vs input frequency frequency (mhz) 0 10 20 30 40 50 60 70 80 90 100 amplitude (db) 1406 g05 0123 4 5 67 8910 f sample = 20mhz f in1 = 3.500977mhz f in2 = 3.598633mhz figure 5. intermodulation distortion plot downloaded from: http:///
10 ltc1406 applicatio n s i n for m atio n wu u u single input providing a 1v bipolar input range centered around a in . likewise, a in + can be tied to a fixed voltage and a in used as the single input. in any configuration the maximum output code (1111 1111) occurs when [(a in + ) ?(a in )] = 1v and the minimum output code (0000 0000) occurs when [(a in + ) ?(a in )] = 1v. each analog input can swing from ground to v dd but not beyond. therefore, the input common mode voltage canrange from 0.5v to 4.5v in differential mode and from 1v to 4v in single-ended mode. as an example, with a in connected to the v ref pin (2.5v) the input range will be 1.5v to 3.5v (see figure 8a). toachieve other ranges the input may be capacitively coupled to achieve a 2v span with virtually any common mode voltage (see figure 8b). the 2v input span requires a 2.5v external reference be connected to the v ref pin. the lt1460-2.5 micropower precision series reference is recommended. to achieveother input spans, the reference voltage (v ref ) can vary between 2v to 3v. the v ref pin can also be driven with a dac or other means. this is useful in applications wherethe peak input signal amplitude may vary. the input span of the adc can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. the analog inputs of the ltc1406 are easy to drive. the inputs draw only one small current spike while charging the sample-and-hold capacitors following a rising clk edge. input frequency (hz) 100k common mode rejection (db) 70 60 50 40 30 20 10 0 1m 10m 100m 1406 g08 figure 7. common mode rejectionvs input frequency figure 8b. ac coupled figure 8a. dc coupled a in + analog input 1.5v to 3.5v 2.5v 1406 f08a a in ltc1406 v ref a in + analog input 2v span 2.5v 1406 f08b a in ltc1406 v ref while clk is low the analog inputs draw only a small leak-age current. if the source impedance of the driving circuit is low, then the ltc1406 inputs can be driven directly. as source impedance increases, so will acquisition time. for minimum acquisition time with high source impedance, a buffer amplifier should be used. the only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 25ns for full throughput rate). choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 50 ) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of1 and has a unity-gain bandwidth of 50mhz, then the out- put impedance at 50mhz must be less than 50 . the second requirement is that the closed-loop bandwidth mustbe greater than 70mhz to ensure adequate small-signal settling for full throughput rate. the following list is a summary of the op amps that are suitable for driving the ltc1406. more detailed informa- tion is available in the linear technology databooks and on the linearview tm cd-rom. lt 1223: 100mhz video current feedback amplifier. 6ma supply current. 5v to 15v supplies. low noise. lt1227: 140mhz video current feedback amplifier. 10ma supply current. 5v to 15v supplies. low distortion. low noise. linearview is a trademark of linear technology corporation. downloaded from: http:///
11 ltc1406 applicatio n s i n for m atio n wu u u lt1229/lt1230: dual and quad 100mhz current feed- back amplifiers. 2v to 15v supplies. low noise. 6ma supply current each amplifier.lt1259/lt1260: dual and triple 130mhz current feed- back amplifiers. 2v to 14v supplies. 5ma supply cur- rent. low distortion. low noise.lt1363: 70mhz voltage feedback amplifier. 2.5v to 15v supplies. 7.5ma supply current. low distortion. lt1364/lt1365: dual and quad 70mhz voltage feedback amplifiers. 2.5v to 15v supplies. 7.5ma supply current per amplifier. low distortion.input filtering the noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the ltc1406 noise and distortion. the small-signal band- width of the sample-and-hold circuit is 250mhz. any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. for example, figure 9 shows a 220pf capacitor from a in + to a in and a 75 source resistor to limit the input bandwidth to 9.6mhz. the 220pf capacitoralso acts as a charge reservoir for the input sample-and- hold and isolates the adc input from sampling glitch sen- sitive circuitry. larger value capacitors may be substituted to further limit the input bandwidth. high quality capaci- tors and resistors should be used since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can also generate distortion from self-heatingand from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. input/output characteristics figure 10 shows the ideal input/output characteristics for the ltc1406. the code transitions occur midway between successive integer lsb values (i.e., fs + 0.5lsb, fs + 1.5lsb, fs + 2.5lsb...fs ?1.5lsb, fs ?0.5lsb). the output is straight binary with 1lsb = fs ?( fs)/256 = 2v/ 256 = 7.8125mv. the of/uf bit indicates that the input has exceeded full scale and can be used to detect an overrange or underrange condition. a logic high output on the of/uf pin with an output code of 0000 0000 indicates the input is less than the negative full scale. a logic high output on the of/uf pin with an output code of 1111 1111 indicates that the input is greater than the positive full scale. a logic low output on the of/uf pin indicates the input is within the full-scale range of the converter. in applications where absolute accuracy is important, off- set and full-scale errors can be adjusted to zero. offset error must be adjusted before full-scale error. zero offset is achieved by adjusting the offset applied to the a in input. for zero offset error, apply a voltage equal to the input figure 10. transfer characteristics figure 9. rc input filter a in + analog input 1.5v to 3.5v 2.5v 220pf 75 1406 f09 a in ltc1406 v ref input voltage (v) 0 output code ? lsb 1406 f10 1111 1111 of/uf bit 1111 11101111 1101 1000 0001 1000 0000 0111 1111 0111 1110 0000 0000 0000 0001 0000 0010 1 lsb fs ?1lsb fs downloaded from: http:///
12 ltc1406 applicatio n s i n for m atio n wu u u while the falling edge starts the conversion, both risingand falling edges are used internally during the conver- sion. it is therefore important to provide a clock signal that has low jitter and fast rise and fall times (< 2ns). much of the internal circuitry operates dynamically limiting the mini- mum conversion rate to 10khz. to ensure proper opera- tion after power is first applied, or the clock stops for more than 100 s, typically 20 clock cycles must be performed at a sample rate above 10khz before the output data willbe valid. common mode voltage minus 3.90625mv (i.e., 0.5lsb) and adjust the offset at the a in input until the output code flickers between 0111 1111 and 1000 0000. for full-scaleadjustment, an input voltage equal to the input common mode voltage plus 988.28125mv (i.e., fs ?1.5lsbs) is applied to a in + and the v ref input is adjusted until the output code flickers between 1111 1110 and 1111 1111.digital inputs and outputs the ltc1406 is designed to easily interface with either 3v or 5v logic. the digital input pins, shdn and clk, have thresholds of nominally 1.9v and will accept a 3v or 5v logic input. the data output pins, including of/uf, are connected to a separate supply and ground (ov dd and ognd respectively). ov dd is normally connected to dv dd but can be connected to an external supply as low as 2.7v.ognd is normally connected to dgnd but can be con- nected to an external ground or an external voltage source as high as 2v. clock the ltc1406 requires a 50% duty cycle clock. the duty cycle should be timed from the nominal threshold of the clk input which is 1.9v. at conversion speeds below the maximum conversion rate of 20mhz, the duty cycle can deviate from 50% with no degradation in performance as long as each clock phase is at least 25ns long. at the maximum conversion rate, deviation from a 50% duty cycle clock results in interstage settling times of < 25ns and performance may be affected. with the clk pin high, the adc will track the difference of the two analog inputs. on the falling edge of clk the input is sampled and the conversion begins. at the end of five clock cycles (on the fifth falling clk edge following the start of conversion) the data from the conversion will be available at the digital outputs until the next falling clk edge. each falling edge of clk starts a new conversion so successive conversion results are available on successive falling clk edges. figure 11. typical dnl vs duty cycle duty cycle (%) 28 dnl (lsbs) 10 9 8 7 6 5 4 3 2 1 0 64 68 1406 f11 36 40 32 44 48 52 56 60 72 f sample = 20mhz power shutdownthe quiescent power of the ltc1406 can be further reduced between conversions by taking the shdn pin low. this powers down all of the internal amplifiers and bias circuitry and the part draws only a small quiescent current of 1 a from the 5v supply. there is a nominally 4k internal resistor between v ref and agnd that will continue to draw current during shutdown as long as v ref is driven. it should also be noted that the data output drivers are not three-state devices and do not go into a high impedance state during shutdown. if the data output pins will remain con- nected to a load during shutdown, current may be drawn through the ov dd supply pin. this can be prevented by including a fet switch in series with ov dd or ognd con- trolled by shdn. if the data bus will remain active during downloaded from: http:///
13 ltc1406 applicatio n s i n for m atio n wu u u microprocessor bus, it is possible to get errors in the con-version results. these errors are due to feedthrough from the microprocessor to the comparators. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. the ltc1406 has differential inputs to minimize noise cou- pling. common mode noise on the a in + and a in leads will be rejected by the input cmrr. the ltc1406 will hold andconvert the difference voltage between a in + and a in . the leads to a in + (pin 7) and a in (pin 8) should be kept as short as possible. in applications where this is not pos-sible, the a in + and a in traces should be run side by side to equalize coupling.supply bypassing high quality, low series resistance ceramic, 10 f bypass capacitors should be used at the v dd , v cm and v ref pins as shown in the typical application on the first page of thisdata sheet. surface mount ceramic capacitors such as murata grm235y5v106z016 provide excellent bypass- ing in a small board space. alternatively, 10 f tantalum capacitors in parallel with 0.1 f ceramic capacitors can be used. bypass capacitors must be located as close to thepins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. example layout figures 12a, 12b, 12c and 12d show the schematic and layout of an evaluation board. the layout demonstrates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board. shutdown. it may also be desirable to isolate the data out-put pins from the bus to reduce the load capacitance. to resume normal operation the shdn pin must be brought high and typically 20 clock cycles must be performed at a sample rate above 10khz before the output data will be valid. board layout and bypassing wire wrap boards are not recommended for high resolu- tion or high speed a/d converters. to obtain the best per- formance from the ltc1406, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. an analog ground plane separate from the logic system ground should be established under and around the adc. pin 1 (ognd), pin 6 (agnd), pin 10 (agnd) and pin 11 (dgnd) and all other analog grounds should be connected to this single analog ground point. the v cm , v ref , dv dd and ov dd bypass capacitors should also be connected to this analog ground plane. no other digital grounds shouldbe connected to this analog ground plane. in some appli- cations it may be desirable to connect the ov dd to the logic system supply and ognd to the logic system ground. inthese cases ov dd should be bypassed to ognd instead of the analog ground plane.low impedance analog and digital power supply common returns are essential to low noise operation of the adc and the foil width for these tracks should be as wide as pos- sible. in applications where the adc data outputs and control signals are connected to a continuously active downloaded from: http:///
14 ltc1406 applicatio n s i n for m atio n wu u u figure 12a. suggested evaluation circuit schematic c9 0.1 f c3, 0.1 f c2 10 f 10v clk c5 0.1 f u1 lt1460-2.5 (ms8) jp3 e4 shdn e5 ext ref j2 a in + j5 (opt) j3 a in j6 (opt) c6 (opt) r5 1k (opt) jp9 jp5 jp4 5v 5v 5v jp7 jp6 r2 10 r6 1k (opt) c8 100pf c13 0.1 f c12 0.1 f oe d0 d1 d2 d3 d4 d5 d6 d7 gnd of/uf d7 d6 d5 d4 d3 d2 d1 d0 clk ognd ognd clk ognd v cc q0 q1 q2 q3 q4 q5 q6 q7 ck 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 20 19 18 17 16 15 14 13 12 11 24 23 22 21 20 19 18 17 16 15 14 13 r11 r3 50 r4 50 r8 50 r10, 1k r1 10 c4 22 f, 10v c17 0.1 f c7 10 f 10v c16 c14 10 f, 10v 1406 f12a u4, 74hc574 (opt) u3 ltc1406 2 3 5 2 3 4 14 5 7 r12 r13r14 r15 r16 r17 r18 r19 51 u2 74hc74 (opt) u7 tc7sh04f r7 1k (opt) v cc v cc j1 clock j4 (opt) e3 output gnd e2 output supply e6 analog ground e1 analog supply jp1 jp12 jp2 c11 10 f 10v c10 0.1 f c15 0.1 f u6 dip8 (opt) u5 so8 (opt) note: all resistors are in ohms, 1/8w, 5%, 0805 c1 22 f 10v jp8 (opt) jp11 jp10 r9 1k 2.5v ref out in 6 23 2 3 2 4 4 4 6 7 6 7 gnd + + 10 f, 10v ognd ov dd shdn v bias v ref agnd ain + ain av dd agnd dgnd dv dd clk of/uf d7 d6 d5 d4 d3 d2 d1 d0 nc nc + + downloaded from: http:///
15 ltc1406 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. applicatio n s i n for m atio n wu u u 0.337 ?0.344* (8.560 ?8.738) gn24 (ssop) 1197 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 9 10 11 12 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 17 18 19 20 21 22 23 24 15 14 13 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.025 (0.635) bsc gn package 24-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) package descriptio n u dimensions in inches (millimeters) unless otherwise noted. figure 12b. suggested evaluation circuitboard?omponent side silkscreen figure 12c. suggested evaluation circuitboard?omponent side layout figure 12d. suggested evaluation circuitboard?older side layout downloaded from: http:///
16 ltc1406 ? linear technology corporation 1998 1406f lt/tp 0299 4k ? printed in usa typical applicatio n u low power, 20mhz, 8-bit sampling adc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ognd ov dd shdn v bias v ref agnd a in + a in av dd agnd dgnd dv dd clk of/uf d7 d6 d5 d4 d3 d2 d1 d0 nc nc ltc1406 10 f nc clock inputoverflow/underflow output nc 1406 ta03 10 f 8-bit parallel bus 10 f 2.5v reference analog inputs 5v part number description comments adcs ltc1196/ltc1198 single supply, 8-bit, 1msps/750ksps adcs single 3v or 5v supply, low power, serial interface, so-8 package ltc1197/ltc1199 single supply, 10-bit, 500ksps/450ksps adcs single 3v or 5v supply, low power, serial interface, so-8 package ltc1410 12-bit, 1.25msps sampling adc with shutdown best dynamic performance, thd = 84db and sinad = 71db at nyquist ltc1415 single 5v, 12-bit, 1.25msps adc single supply 55mw dissipation ltc1419 14-bit, 800ksps sampling adc with shutdown 81.5db sinad, 150mw from 5v supplies ltc1604 16-bit, 333ksps adc 90db sinad, 100db thd, 250mw dissipation ltc1605 single 5v, 16-bit, 100ksps adc low power, 10v inputs dacs ltc1446/ltc1446l dual 12-bit v out dacs in so-8 package ltc1446: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1446l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1448 dual 12-bit rail-to-rail output dac in so-8 package v cc = 2.7v to 5.5v, output swings from gnd to ref, ref input can be tied to v cc ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs ltc1458: v cc = 4.5v to 5.5v, v out 0v to 4.095v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear-tech.com related parts downloaded from: http:///

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